Efficient, high quality work of Akos Szoboszlay, BS EE

Why it often takes me half the time, or less, as an average engineer to complete a project, including design, debug, test and documentation. (See examples, below.)

Many times, I was hired for a job because the engineers at the company were unable to get their circuit board or system/product to work. Most of these times, the design was so bad I had to redesign, yet I finished in a fraction of the time taken by the original engineer(s), including documentation (which they did not do). The reasons for this are:

• I have the extensive experience to know which technology to use (e.g., a CPLD designed in HDL instead of a 500-state state-machine EPROM programmed in 0s and 1s).
• I have the engineering experience not to make many of the mistakes I've seen people make. Extreme examples I've seen were when digital designers tried to do an analog design, and when technicians tried to do an FPGA design, then simply were unable to get their designs to work.
• I have a rapport with software/firmware, writing detailed specs, using pseudo-code for complicated logic. When they got stuck with the debug, I've solved difficult problems by setting up the logic analyzer and/or inverse assembler, and found the error in the code. (For some jobs, I even wrote the code in addition to hardware design).
• I have great communication skills, both verbal and in writing. Formerly, I was a volunteer newsletter editor and wrote many articles. I have significant accomplishments in the political arena which required good verbal and written communication skills.
• I am well organized, and keep project do lists. I work on a project's critical-path-flow basis.
• I document while I do the design, instead of doing all of it afterwards as is common. This contributes to keeping organized and reduces errors. If written specs are not provided, I write them and have them approved by management before I start the design -- usually taking a few iterations.
• I select optimized components for the design -- which depend on the project design criteria of reliability, size, design time, arrival of part, multiple sources, price, etc. I know what technology to use, (e.g., JFET input op amp for high frequency, low current, low noise) but also use on-line parametric search tables to make sure I cover any new developments.
• I design for testability, placing test points for grounds and test equipment, test plugs, and often write my own test programs. I write the test procedure and calibration procedure before I go to fabrication stage, because writing those usually shows where I need to add some test points, bring out signals, etc.
• I know how to use many types of equipment such as a Dynamic Signal Analyzer which few EEs know how to use.
• I know how to do low noise analog design which requires many techniques at different design levels. [See my article.] Not applying these techniques causes problems and schedule delays.
• Before starting the design, I take an overview. I start the detailed design when there are no major unknowns in architecture or sensor type, because those unknowns can greatly effect the details. I then do a top-down design. In contrast, I have seen designs of others where the engineer designs and builds (fab, assembly, test) one section without considering other sections, then does likewise for the next section, etc., resulting in the sections not connecting together in an efficient and logical manner, and requiring more circuitry, cabling, and total design time. This method further delays the schedule because portions have to be re-designed to get the system/product to work as a whole.
• Last but maybe most importantly, I am a good designer knowing simplicity usually gives a better and faster design than a brute-force approach that would work but takes more design time and circuits. Before starting the detailed design, I find it is worth taking time to see how much the "problem" or "task" can be simplified. Here is a simple example:
  At Maxspeed Inc., I redesigned a FIFO in an FPGA while another engineer, in an earlier design, used a complicated state-machine to obtain the full and empty status of the FIFO. I placed an extra bit into the write and read address pointers before subtracting them:
  difference = 0 meant empty and difference MSB = 1 meant full.
  This was an elegant mathematical solution that saved not only logic, but also design and debug time because it was so simple.

Examples of the above

• At Abbott Laboratories, I completed the largest circuit board in the system (design, build, debug, rework, test, document) in one fabrication cycle due to my low error rate, and met the schedule for obtaining clinical data in the medical product. I have error finding techniques using various checking procedures. Other engineers, in contrast, had two or more fabrication cycles.
• At Nikon Research (NRCA), after completing my project, I solved an intermittent bad data problem on another project which the company had not been able to solve in one year. This task took me about one week.
• At Digital Microwave, the designers could not get the circuit board (a 68302 based design) to work, and a consultant could not get it to work in 4 weeks. They hired me and I solved over a half dozen design and artwork routing errors. I had the core (uP, RAM, EPROM, Flash, DUART, PIA, etc.) working in 2 weeks (using rework only !). I re-designed the rest of the board (e.g., ADC, DAC and phone chips) which required a new FAB. My ADC and DAC designs not only worked right off (after debugging my assembly language drivers), they were also cheaper than used in the earlier design. I used serial ADC and serial DAC, taking advantage of the unused 3-wire port on the 68302 processor chip. And, I didn't load the uP bus any further.
• Also at Digital Microwave, I wrote not only the test program for the board in C language, but the stripped-down version of the real-time program for a customer demo. The latter took me only two weeks, and amazed the manager.
• At Compression Labs, I took 4 months and one circuit board FAB to complete an MPEG and Digital Video design in what the previous designer could not complete in over a year using 3 FABs.
• At Memorex, I completed a 3-board analog/digital design in 2 months what the previous designer could not do in 1 year. (They did say he was fresh out of college.)